RISC-V CPU
VHDLBuilding a RISC-V CPU with an ALU, register file, and control logic.
Experience with VHDL, logic design, timing, and simulation.
I’m a third-year Computer Science student at Wilfrid Laurier University interested in low-level systems, computer networks, and RISC-V CPU design.
Building a RISC-V CPU with an ALU, register file, and control logic.
Experience with VHDL, logic design, timing, and simulation.
Exploring routing, congestion, sockets, and packet-level behavior.
Roles in systems, networking,cloud computing roles, infrastructure, or hardware-adjacent software.
A few things I’ve been working on recently.
Full 32-bit RISC-V CPU emulator that fetches, decodes, and executes real instructions.
Client-server networking application using raw TCP/UDP sockets.
Selected assignments from systems, algorithms, and digital logic courses.
Reserved for an upcoming systems or networking project.
Full resume available as a PDF.
Third-year CS student specializing in systems, networks, and hardware-adjacent programming.
Technical Skills
Key Coursework